Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics

ABSTRACT

A dielectric film containing HfO 2 /ZrO 2  nanolaminates and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO 2 . A gate dielectric is formed by atomic layer deposition of HfO 2  using a HfI 4  precursor followed by the formation of ZrO 2  on the HfO 2  layer.

RELATED APPLICATIONS

The present application is a Divisional of U.S. application Ser. No.10/209,581, filed Jul. 30, 2002, which is incorporated herein byreference.

This application is related to the following, co-pending, commonlyassigned applications, incorporated herein by reference:

-   -   U.S. application Ser. No. 10/163,481, entitled: “Atomic        Layer-Deposited HfAlO₃ Films for Gate Dielectrics;”    -   U.S. application Ser. No. 10/137,499, entitled: “Atomic        Layer-Deposited LaAlO₃ Films for Gate Dielectrics;”    -   U.S. application Ser. No. 10/137,058, entitled: “Atomic Layer        Deposition and Conversion;”    -   U.S. application Ser. No. 09/945,535, entitled: “Highly Reliable        Amorphous High-K Gate Oxide ZrO₂;”    -   U.S. application Ser. No. 10/137,168, entitled: “Methods,        Systems, and Apparatus for Atomic-Layer Deposition of Aluminum        Oxides in Integrated Circuits;” and    -   U.S. Pat. No. 6,852,167, entitled: “Methods, Systems, and        Apparatus for Uniform Chemical-Vapor Depositions.”

FIELD OF THE INVENTION

The invention relates to semiconductor devices and device fabrication.Specifically, the invention relates to gate dielectric layers oftransistor devices and their method of fabrication.

BACKGROUND OF THE INVENTION

The semiconductor device industry has a market driven need to improvespeed performance, improve its low static (off-state) powerrequirements, and adapt to a wide range of power supply and outputvoltage requirements for it silicon based microelectronic products. Inparticular, in the fabrication of transistors, there is continuouspressure to reduce the size of devices such as transistors. The ultimategoal is to fabricate increasingly smaller and more reliable integratedcircuits (ICs) for use in products such as processor chips, mobiletelephones, or memory devices such as DRAMs. The smaller devices arefrequently powered by batteries, where there is also pressure to reducethe size of the batteries, and to extend the time between batterycharges. This forces the industry to not only design smallertransistors, but to design them to operate reliably with lower powersupplies.

Currently, the semiconductor industry relies on the ability to reduce orscale the dimensions of its basic devices, primarily, the silicon basedmetal-oxide-semiconductor field effect transistor (MOSFET). A commonconfiguration of such a transistor is shown in FIG. 1. While thefollowing discussion uses FIG. 1 to illustrate a transistor from theprior art, one skilled in the art will recognize that the presentinvention could be incorporated into the transistor shown in FIG. 1 toform a novel transistor according to the invention. The transistor 100is fabricated in a substrate 110 that is typically silicon, but could befabricated from other semiconductor materials as well. The transistor100 has a first source/drain region 120 and a second source/drain region130. A body region 132 is located between the first source/drain regionand the second source/drain region, where the body region 132 defines achannel of the transistor with a channel length 134. A gate dielectric,or gate oxide 140 is located on the body region 132 with a gate 150located over the gate dielectric. Although the gate dielectric can beformed from materials other than oxides, the gate dielectric istypically an oxide, and is commonly referred to as a gate oxide. Thegate may be fabricated from polycrystalline silicon (polysilicon), orother conducting materials such as metal may be used.

In fabricating transistors to be smaller in size and reliably operate onlower power supplies, one important design criteria is the gatedielectric 140. The mainstay for forming the gate dielectric has beensilicon dioxide, SiO₂. A thermally grown amorphous SiO₂ layer providesan electrically and thermodynamically stable material, where theinterface of the SiO₂ layer with underlying Si provides a high qualityinterface as well as superior electrical isolation properties. Intypical processing, use of SiO₂ on Si has provided defect chargedensities on the order of 10¹⁰/cm², midgap interface state densities ofapproximately 10¹⁰/cm² eV, and breakdown voltages in the range of 15MV/cm. With such qualities, there would be no apparent need to use amaterial other than SiO₂, but increased scaling and other requirementsfor gate dielectrics create the need to find other dielectric materialsto be used for a gate dielectric.

What is needed is an alternate dielectric material for forming a gatedielectric that has a high dielectric constant relative to SiO₂, and isthermodynamically stable with respect to silicon such that forming thedielectric on a silicon layer will not result in SiO₂ formation, ordiffusion of material, such as dopants, into the gate dielectric fromthe underlying silicon layer.

SUMMARY OF THE INVENTION

A solution to the problems as discussed above is addressed inembodiments according to the teachings of the present invention. In oneembodiment, a method of forming a gate dielectric on a transistor bodyregion includes the formation of HfO₂/ZrO₂ nanolaminates by atomic layerdeposition (ALD) of HfO₂ using a HfI₄ precursor followed by theformation of ZrO₂ on the HfO₂ layer. Various embodiments include formingthe ZrO₂ layer by thermal evaporation followed by krypton/oxygen mixedplasma oxidation, pulsed-laser deposition, or jet-vapor deposition.

A gate dielectric formed as nanolaminates of HfO₂/ZrO₂ has a largerdielectric constant than silicon dioxide, a relatively small leakagecurrent, and good stability with respect to a silicon based substrate.Embodiments according to the teachings of the present invention includeforming transistors, memory devices, and electronic systems havingdielectric layers containing nanolaminates of HfO₂/ZrO₂.

Other embodiments include structures for transistors, memory devices,and electronic systems with gate dielectrics containing nanolaminates ofHfO₂/ZrO₂. Such gate dielectrics provide a significantly thinnerequivalent oxide thickness compared with a silicon oxide gate having thesame physical thickness. Alternatively, such gate dielectrics provide asignificantly thicker physical thickness than a silicon oxide gatedielectric having the same equivalent oxide thickness.

These and other embodiments, aspects, advantages, and features of thepresent invention will be set forth in part in the description whichfollows, and in part will become apparent to those skilled in the art byreference to the following description of the invention and referenceddrawings or by practice of the invention. The aspects, advantages, andfeatures of the invention are realized and attained by means of theinstrumentalities, procedures, and combinations particularly pointed outin the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a common configuration of a transistor in which anembodiment of a gate dielectric can be formed, according to the teachingof the present invention.

FIG. 2A shows an embodiment of an atomic layer deposition system forprocessing a layer of HfO₂ and a nanolaminate of HfO₂/ZrO₂, according tothe teachings of the present invention.

FIG. 2B shows an embodiment of a gas-distribution fixture of an atomiclayer deposition chamber for processing a layer of HfO₂ and ananolaminate of HfO₂/ZrO₂, according to the teachings of the presentinvention.

FIG. 3 illustrates a flow diagram of elements for an embodiment of amethod to process a nanolaminate of HfO₂/ZrO₂, according to theteachings of the present invention.

FIG. 4 illustrates a flow diagram of elements for another embodiment ofa method to process a nanolaminate of HfO₂/ZrO₂ by atomic layerdeposition, according to the teachings of the present invention.

FIG. 5 illustrates a flow diagram of elements for an embodiment of amethod to process a nanolaminate of HfO₂/ZrO₂ using atomic layerdeposition and thermal evaporation/plasma oxidation, according to theteachings of the present invention.

FIG. 6 shows an embodiment of an electron beam evaporation process forforming a layer of zirconium on a layer of HfO₂ to process ananolaminate of HfO₂/ZrO₂, according to the teachings of the presentinvention.

FIG. 7A shows an embodiment of a zirconium layer deposited on a layer ofHfO₂, according to the teachings of the present invention.

FIG. 7B shows an embodiment of a partially oxidized zirconium layerdeposited on a layer of HfO₂, according to the teachings of the presentinvention.

FIG. 7C shows an embodiment of a ZrO₂ substantially completely oxidizedand formed on a layer of HfO₂ to form a nanolaminate of HfO₂/ZrO₂,according to the teachings of the present invention.

FIG. 8 illustrates a flow diagram of elements for an embodiment of amethod to process a nanolaminate of HfO₂/ZrO₂ using atomic layerdeposition and chemical vapor deposition, according to the teachings ofthe present invention.

FIG. 9 illustrates a flow diagram of elements for an embodiment of amethod to process a nanolaminate of HfO₂/ZrO₂ using atomic layerdeposition and pulsed-laser deposition, according to the teachings ofthe present invention.

FIG. 10 illustrates a flow diagram of elements for an embodiment of amethod to process a nanolaminate of HfO₂/ZrO₂ using atomic layerdeposition and jet-vapor deposition, according to the teachings of thepresent invention.

FIG. 11 shows an embodiment of a configuration of a transistor capableof being fabricated, according to the teachings of the presentinvention.

FIG. 12 shows an embodiment of a personal computer incorporatingdevices, according to the teachings of the present invention.

FIG. 13 illustrates a schematic view of an embodiment of a centralprocessing unit incorporating devices, according to the teachings of thepresent invention.

FIG. 14 illustrates a schematic view of an embodiment of a DRAM memorydevice, according to the teachings of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description of the invention, reference ismade to the accompanying drawings which form a part hereof, and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. These embodiments are described insufficient detail to enable those skilled in the art to practice theinvention. Other embodiments may be utilized and structural, logical,and electrical changes may be made without departing from the scope ofthe present invention.

The terms wafer and substrate used in the following description includeany structure having an exposed surface with which to form theintegrated circuit (IC) structure of the invention. The term substrateis understood to include semiconductor wafers. The term substrate isalso used to refer to semiconductor structures during processing, andmay include other layers that have been fabricated thereupon. Both waferand substrate include doped and undoped semiconductors, epitaxialsemiconductor layers supported by a base semiconductor or insulator, aswell as other semiconductor structures well known to one skilled in theart. The term conductor is understood to include semiconductors, and theterm insulator or dielectric is defined to include any material that isless electrically conductive than the materials referred to asconductors.

The term “horizontal” as used in this application is defined as a planeparallel to the conventional plane or surface of a wafer or substrate,regardless of the orientation of the wafer or substrate. The term“vertical” refers to a direction perpendicular to the horizontal asdefined above. Prepositions, such as “on”, “side” (as in “sidewall”),“higher”, “lower”, “over” and “under” are defined with respect to theconventional plane or surface being on the top surface of the wafer orsubstrate, regardless of the orientation of the wafer or substrate. Thefollowing detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the appended claims, along with the full scope of equivalents towhich such claims are entitled.

A gate dielectric 140 of FIG. 1, when operating in a transistor, hasboth a physical gate dielectric thickness and an equivalent oxidethickness (t_(eq)). The equivalent oxide thickness quantifies theelectrical properties, such as capacitance, of a gate dielectric 140 interms of a representative physical thickness. t_(eq) is defined as thethickness of a theoretical SiO₂ layer that would be required to have thesame capacitance density as a given dielectric, ignoring leakage currentand reliability considerations.

A SiO₂ layer of thickness, t, deposited on a Si surface as a gatedielectric will have a t_(eq) larger than its thickness, t. This t_(eq)results from the capacitance in the surface channel on which the SiO₂ isdeposited due to the formation of a depletion/inversion region. Thisdepletion/inversion region can result in t_(eq) being from 3 to 6Angstroms (Å) larger than the SiO₂ thickness, t. Thus, with thesemiconductor industry driving to someday scale the gate dielectricequivalent oxide thickness to under 10 Å, the physical thicknessrequirement for a SiO₂ layer used for a gate dielectric would be need tobe approximately 4 to 7 Å.

Additional requirements on a SiO₂ layer would depend on the gateelectrode used in conjunction with the SiO₂ gate dielectric. Using aconventional polysilicon gate would result in an additional increase int_(eq) for the SiO₂ layer. This additional thickness could be eliminatedby using a metal gate electrode, though metal gates are not currentlyused in complementary metal-oxide-semiconductor field effect transistor(CMOS) technology. Thus, future devices would be designed towards aphysical SiO₂ gate dielectric layer of about 5 Å or less. Such a smallthickness requirement for a SiO₂ oxide layer creates additionalproblems.

Silicon dioxide is used as a gate dielectric, in part, due to itselectrical isolation properties in a SiO₂—Si based structure. Thiselectrical isolation is due to the relatively large band gap of SiO₂(8.9 eV) making it a good insulator from electrical conduction.Signification reductions in its band gap would eliminate it as amaterial for a gate dielectric. As the thickness of a SiO₂ layerdecreases, the number of atomic layers, or monolayers of the material inthe thickness decreases. At a certain thickness, the number ofmonolayers will be sufficiently small that the SiO₂ layer will not havea complete arrangement of atoms as in a larger or bulk layer. As aresult of incomplete formation relative to a bulk structure, a thin SiO₂layer of only one or two monolayers will not form a full band gap. Thelack of a full band gap in a SiO₂ gate dielectric would cause aneffective short between an underlying Si channel and an overlyingpolysilicon gate. This undesirable property sets a limit on the physicalthickness to which a SiO₂ layer can be scaled. The minimum thickness dueto this monolayer effect is thought to be about 7-8 Å. Therefore, forfuture devices to have a t_(eq) less than about 10 Å, other dielectricsthan SiO₂ need to be considered for use as a gate dielectric.

For a typical dielectric layer used as a gate dielectric, thecapacitance is determined as one for a parallel plate capacitance:C=κ∈₀A/t, where κ is the dielectric constant, ∈₀ is the permittivity offree space, A is the area of the capacitor, and t is the thickness ofthe dielectric. The thickness, t, of a material is related to t_(eq) fora given capacitance with the dielectric constant of SiO₂, κ_(ox)=3.9,associated with t_(eq), ast=(κ/κ_(ox))t _(eq)=(κ/3.9)t _(eq).Thus, materials with a dielectric constant greater than that of SiO₂,3.9, will have a physical thickness that can be considerably larger thana desired t_(eq), while providing the desired equivalent oxidethickness. For example, an alternate dielectric material with adielectric constant of 10 could have a thickness of about 25.6 Å toprovide a t_(eq) of 10 Å, not including any depletion/inversion layereffects. Thus, the reduced equivalent oxide thickness of transistors canbe realized by using dielectric materials with higher dielectricconstants than SiO₂.

The thinner equivalent oxide thickness required for lower transistoroperating voltages and smaller transistor dimensions may be realized bya significant number of materials, but additional fabricatingrequirements makes determining a suitable replacement for SiO₂difficult. The current view for the microelectronics industry is stillfor Si based devices. This requires that the gate dielectric employed begrown on a silicon substrate or silicon layer, which places significantrestraints on the substitute dielectric material. During the formationof the dielectric on the silicon layer, there exists the possibilitythat a small layer of SiO₂ could be formed in addition to the desireddielectric. The result would effectively be a dielectric layerconsisting of two sublayers in parallel with each other and the siliconlayer on which the dielectric is formed. In such a case, the resultingcapacitance would be that of two dielectrics in series. As a result, thet_(eq) of the dielectric layer would be the sum of the SiO₂ thicknessand a multiplicative factor of the thickness of the dielectric beingformed, written ast _(eq) =t _(SiO2)+(κ_(ox)/κ)t.Thus, if a SiO₂ layer is formed in the process, the t_(eq) is againlimited by a SiO₂ layer. In the event that a barrier layer is formedbetween the silicon layer and the desired dielectric in which thebarrier layer prevents the formation of a SiO₂ layer, the t_(eq) wouldbe limited by the layer with the lowest dielectric constant. However,whether a single dielectric layer with a high dielectric constant or abarrier layer with a higher dielectric constant than SiO₂ is employed,the layer interfacing with the silicon layer must provide a high qualityinterface to maintain a high channel carrier mobility.

In a recent article by G. D. Wilk et al., Journal of Applied Physics,vol. 89: no. 10, pp. 5243-5275 (2001), material properties of highdielectric materials for gate dielectrics were discussed. Among theinformation disclosed was the viability of Al₂O₃ as a substitute forSiO₂. Al₂O₃ was disclosed has having favourable properties for use as agate dielectric such as high band gap, thermodynamic stability on Si upto high temperatures, and an amorphous structure. In addition, Wilkdisclosed that forming a layer of Al₂O₃ on silicon does not result in aSiO₂ interfacial layer. However, the dielectric constant of Al₂O₃ isonly 9, where thin layers may have a dielectric constant of about 8 toabout 10. Though the dielectric constant of Al₂O₃ is in an improvementover SiO₂, a higher dielectric constant for a gate dielectric isdesirable. Other dielectrics and their properties discussed by Wilkinclude Dielectric Band gap Crystal Material Constant (κ) E_(g) (eV)Structure(s) SiO₂ 3.9 8.9 Amorphous Si₃N₄ 7 5.1 Amorphous Al₂O₃ 9 8.7Amorphous Y₂O₃ 15 5.6 Cubic La₂O₃ 30 4.3 Hexagonal, Cubic Ta₂O₅ 26 4.5Orthorhombic TiO2 80 3.5 Tetrag. (rutile, anatase) HfO₂ 25 5.7 Mono.,Tetrag., Cubic ZrO₂ 25 7.8 Mono., Tetrag., Cubic

One of the advantages using SiO₂ as a gate dielectric has been that theformation of the SiO₂ layer results in an amorphous gate dielectric.Having an amorphous structure for a gate dielectric is advantageousbecause grain boundaries in polycrystalline gate dielectrics providehigh leakage paths. Additionally, grain size and orientation changesthroughout a polycrystalline gate dielectric can cause variations in thefilm's dielectric constant. The abovementioned material propertiesincluding crystal structure are for the materials in a bulk form. Thematerials having the advantage of a high dielectric constants relativeto SiO₂ also have the disadvantage of a crystalline form, at least in abulk configuration. The best candidates for replacing SiO₂ as a gatedielectric are those with high dielectric constant, which can befabricated as a thin layer with an amorphous form.

In an embodiment according to the teachings of the present invention, agate dielectric includes thin layers of HfO₂ and ZrO₂ forming ananolaminate. The term “nanolaminate” means a composite film of ultrathin layers of two or more materials in a layered stack, where thelayers are alternating layers of materials of the composite film.Typically, nanolaminates have thicknesses of an order of magnitude inthe nanometer range. Each individual material layer of the nanolaminatecan have thicknesses as low as a monolayer of the material. Ananolaminate of HfO₂ and ZrO₂ includes at least one thin layer of HfO₂,and one thin layer of ZrO₂, and is typically written as a nanolaminateof HfO₂/ZrO₂. In one embodiment, nanolaminates of HfO₂/ZrO₂ are grownusing atomic layer deposition (ALD), also known as atomic layer epitaxy(ALE).

ALD was developed in the early 1970's as a modification of chemicalvapor deposition (CVD) and is also called “alternatively pulsed-CVD.” InALD, gaseous precursors are introduced one at a time to the substratesurface mounted within a reaction chamber (or reactor). Thisintroduction of the gaseous precursors takes the form of pulses of eachgaseous precursor. Between the pulses, the reaction chamber is purgedwith a gas, which in many cases is an inert gas, or evacuated.

In a chemisorption-saturated ALD (CS-ALD) process, during the firstpulsing phase, reaction with the substrate occurs with the precursorsaturatively chemisorbed at the substrate surface. Subsequent pulsingwith a purging gas removes precursor excess from the reaction chamber.

The second pulsing phase introduces another precursor on the substratewhere the growth reaction of the desired film takes place. Subsequent tothe film growth reaction, reaction byproducts and precursor excess arepurged from the reaction chamber. With favourable precursor chemistrywhere the precursors adsorb and react with each other on the substrateaggressively, one ALD cycle can be preformed in less than one second inproperly designed flow type reaction chambers. Typically, precursorpulse times range from about 0.5 sec to about 2 to 3 seconds.

In ALD, the saturation of all the reaction and purging phases makes thegrowth self-limiting. This self-limiting growth results in large areauniformity and conformality, which has important applications for suchcases as planar substrates, deep trenches, and in the processing ofporous silicon and high surface area silica and alumina powders.Significantly, ALD provides for controlling film thickness in astraightforward, simple manner by controlling the number of growthcycles.

ALD was originally developed to manufacture luminescent and dielectricfilms needed in electroluminescent displays. Significant efforts havebeen made to apply ALD to the growth of doped zinc sulfide and alkalineearth metal sulfide films. Additionally, ALD has been studied for thegrowth of different epitaxial II-V and II-VI films, nonepitaxialcrystalline or amorphous oxide and nitride films and multilayerstructures of these. There also has been considerable interest towardsthe ALD growth of silicon and germanium films, but due to the difficultprecursor chemistry, this has not been very successful.

The precursors used in an ALD process may be gaseous, liquid or solid.However, liquid or solid precursors must be volatile. The vapor pressuremust be high enough for effective mass transportation. Also, solid andsome liquid precursors need to be heated inside the reaction chamber andintroduced through heated tubes to the substrates. The necessary vaporpressure must be reached at a temperature below the substratetemperature to avoid the condensation of the precursors on thesubstrate. Due to the self-limiting growth mechanisms of ALD, relativelylow vapor pressure solid precursors can be used though evaporation ratesmay somewhat vary during the process because of changes in their surfacearea.

There are several other requirements for precursors used in ALD. Theprecursors must be thermally stable at the substrate temperature becausetheir decomposition would destroy the surface control and accordinglythe advantages of the ALD method which relies on the reactant of theprecursor at the substrate surface. Of course, a slight decomposition,if slow compared to the ALD growth, can be tolerated.

The precursors have to chemisorb on or react with the surface, thoughthe interaction between the precursor and the surface as well as themechanism for the adsorption is different for different precursors. Themolecules at the substrate surface must react aggressively with thesecond precursor to form the desired solid film. Additionally,precursors should not react with the film to cause etching, andprecursors should not dissolve in the film. Using highly reactiveprecursors in ALD contrasts with the selection of precursors forconventional CVD.

The by-products in the reaction must be gaseous in order to allow theireasy removal from the reaction chamber. Further, the by-products shouldnot react or adsorb on the surface.

In a reaction sequence ALD (RS-ALD) process, the self-limiting processsequence involves sequential surface chemical reactions. RS-ALD relieson chemistry between a reactive surface and a reactive molecularprecursor. In an RS-ALD process, molecular precursors are pulsed intothe ALD reaction chamber separately. The metal precursor reaction at thesubstrate is typically followed by an inert gas pulse to remove excessprecursor and by-products from the reaction chamber prior to pulsing thenext precursor of the fabrication sequence.

By RS-ALD, films can be layered in equal metered sequences that are allidentical in chemical kinetics, deposition per cycle, composition, andthickness. RS-ALD sequences generally deposit less than a full layer percycle. Typically, a deposition or growth rate of about 0.25 to about2.00 Å per RS-ALD cycle can be realized.

The advantages of RS-ALD include continuity at an interface,conformality over a substrate, use of low temperature and mildlyoxidizing processes, growth thickness dependent solely on the number ofcycles performed, and ability to engineer multilayer laminate films withresolution of one to two monolayers. RS-ALD allows for depositioncontrol on the order on monolayers and the ability to deposit monolayersof amorphous films.

RS-ALD processes provide for the formation of nanolaminates. Thesenanolaminates can be engineered in various forms. In one form, thetransition between material layers of the nanolaminate can be madeabrupt. In another form, the transition between material layers of thenanolaminate can be constructed with a graded composition. The gradedcomposition can be formed by RS-ALD due its control of the depositionthickness per cycle.

In an embodiment, a layer of HfO₂ is formed on a substrate mounted in areaction chamber using ALD in a repetitive sequence including pulsing ahafnium containing precursor into the reaction chamber followed bypulsing a purging gas, and then pulsing a first oxygen containingprecursor into the chamber. In one embodiment using ALD, a layer of HfO₂is formed using HfI₄ as a hafnium containing precursor, water vapor as afirst oxygen containing precursor, and nitrogen as a purging gas andcarrier gas. After forming a HfO₂ layer, a ZrO₂ layer is formed on theHfO₂ layer.

In one embodiment, the layer of ZrO₂ is formed by ALD. In particular, arepetitive sequence includes using ZrI₄ as a zirconium containingprecursor along with a vapor solution of HO₂—H₂O₂ as a second oxygencontaining precursor, and nitrogen as a purging gas and carrier gas. Inanother embodiment, the ZrO₂ layer is formed by depositing a layer ofzirconium on the HfO₂ layer by thermal evaporation, and oxidizing thezirconium layer using a krypton(Kr)/oxygen(O₂) mixed plasma to form aHfO₂/ZrO₂ composite layer. In another embodiment, the ZrO₂ layer isformed by pulsed-laser deposition. In yet another embodiment, the ZrO₂layer is formed by jet-vapor deposition.

In one embodiment, precursor gases, in particular HfI₄, are used to formthe HfO₂ layer for the HfO₂/ZrO₂ nanolaminate films used as a gatedielectric on a transistor body. Alternately, solid or liquid precursorscan be used in an appropriately designed reaction chamber. ALD formationof other materials is disclosed in co-pending, commonly assigned U.S.patent application: entitled “Atomic Layer Deposition and Conversion,”attorney docket no. 303.802US1, Ser. No. 10/137,058, and “Methods,Systems, and Apparatus for Atomic-Layer Deposition of Aluminum Oxides inIntegrated Circuits,” attorney docket no. 1303.048US1, Ser. No.10/137,168.

FIG. 2A shows an embodiment of an atomic layer deposition system forprocessing layers of HfO₂ and nanolaminates of HfO₂/ZrO₂ according tothe teachings of the present invention. The elements depicted are thoseelements necessary for discussion of the present invention such thatthose skilled in the art may practice the present invention withoutundue experimentation. A further discussion of the ALD reaction chambercan be found in co-pending, commonly assigned U.S. patent application:entitled “Methods, Systems, and Apparatus for Uniform Chemical-VaporDepositions,” attorney docket no. 303.717US1, Ser. No. 09/797,324,incorporated herein by reference.

In FIG. 2A, a substrate 210 is located inside a reaction chamber 220 ofALD system 200. Also located within the reaction chamber 220 is aheating element 230 which is thermally coupled to substrate 210 tocontrol the substrate temperature. A gas-distribution fixture 240introduces precursor gases to the substrate 210. Each precursor gasoriginates from individual gas sources 251-254 whose flow is controlledby mass-flow controllers 256-259, respectively. The gas sources 251-254provide a precursor gas either by storing the precursor as a gas or byproviding a location and apparatus for evaporating a solid or liquidmaterial to form the selected precursor gas.

Also included in the ALD system are purging gas sources 261, 262, eachof which is coupled to mass-flow controllers 266, 267, respectively. Thegas sources 251-254 and the purging gas sources 261-262 are coupled bytheir associated mass-flow controllers to a common gas line or conduit270 which is coupled to the gas-distribution fixture 240 inside thereaction chamber 220. Gas conduit 270 is also coupled to vacuum pump, orexhaust pump, 281 by mass-flow controller 286 to remove excess precursorgases, purging gases, and by-product gases at the end of a purgingsequence from the gas conduit.

Vacuum pump, or exhaust pump, 282 is coupled by mass-flow controller 287to remove excess precursor gases, purging gases, and by-product gases atthe end of a purging sequence from the reaction chamber 220. Forconvenience, control displays, mounting apparatus, temperature sensingdevices, substrate maneuvering apparatus, and necessary electricalconnections as are known to those skilled in the art are not shown inFIG. 2A.

FIG. 2B shows an embodiment of a gas-distribution fixture of an atomiclayer deposition chamber for processing layers of HfO₂ and nanolaminatesof HfO₂/ZrO₂, according to the teachings of the present invention.Gas-distribution fixture 240 includes a gas-distribution member 242, anda gas inlet 244. Gas inlet 244 couples the gas-distribution member 242to the gas conduit 270 of FIG. 2A. Gas-distribution member 242 includesgas-distribution holes, or orifices, 246 and gas-distribution channels248. In the exemplary embodiment, holes 246 are substantially circularwith a common diameter in the range of 15-20 microns, gas-distributionchannels 248 have a common width in the range of 20-45 microns. Thesurface 249 of the gas distribution member having gas-distribution holes246 is substantially planar and parallel to the substrate 210 of FIG.2A. However, other embodiments use other surface forms as well as shapesand sizes of holes and channels. The distribution and size of holes mayalso affect deposition thickness and thus might be used to assistthickness control. Holes 246 are coupled through gas-distributionchannels 248 to gas inlet 244. Though the ALD system 200 is well suitedfor practicing the present invention, other ALD systems commerciallyavailable can be used.

The use, construction and fundamental operation of reaction chambers fordeposition of films are understood by those of ordinary skill in the artof semiconductor fabrication. The present invention man be practiced ona variety of such reaction chambers without undue experimentation.Furthermore, one of ordinary skill in the art will comprehend thenecessary detection, measurement, and control techniques in the art ofsemiconductor fabrication upon reading the disclosure.

FIG. 3 illustrates a flow diagram of elements for an embodiment of amethod to process a nanolaminate of HfO₂/ZrO₂, according to theteachings of the present invention. This embodiment of a method forforming a HfO₂/ZrO₂ nanolaminate includes forming a layer of hafniumoxide on a substrate in a reaction chamber by atomic layer depositionusing a HfI₄ precursor, at block 305, and forming a layer of zirconiumoxide on the layer of hafnium oxide to form a HfO₂/ZrO₂ composite, atblock 310. By strictly controlling the processing of the HfO₂ layer andthe ZrO₂ layer, the HfO₂/ZrO₂ composite formed is a HfO₂ZrO₂nanolaminate. In one embodiment, the HfO₂/ZrO₂ nanolaminate is composedof one HfO₂ layer and one layer ZrO₂ layer. In another embodiment, theHfO₂/ZrO₂ nanolaminate includes multiple layers of the HfO₂ZrO₂composite, where the initial layer disposed on a substrate is a HfO₂layer. After this initial HfO₂ layer, there are alternating layers ofHfO₂ and ZrO₂, with the terminating layer being a ZrO₂ layer in oneembodiment and HfO₂ layer in another embodiment.

Forming the HfO₂ layer on a substrate by atomic layer depositioninvolves using a deposition sequence including pulsing the HfI₄precursor into the reaction chamber, followed by pulsing a purging gas,pulsing a first oxygen containing precursor, and pulsing the purginggas. In one embodiment, the first oxygen precursor is water vapor. Eachprecursor is pulsed for a short time ranging from 0.5 seconds to two orthree seconds. A purging gas such as nitrogen is pulsed for a longerperiod such as five to fifteen seconds to insure that all excessprecursor gases and by-products are removed from the reaction chamber.Pulsing times are selected to enable the controlled growth of the HfO₂layer on a one to two monolayer basis. For a fixed ALD sequence orcycle, including fixed pulsing times and substrate temperatures, theHfO₂ layer growth rate is at a relatively fixed rate, where a desiredthickness of the HfO₂ layer is obtained by performing the ALD sequencefor a predetermined number of cycles.

FIG. 4 illustrates a flow diagram of elements for another embodiment ofa method to process a nanolaminate of HfO₂/ZrO₂ by atomic layerdeposition, according to the teachings of the present invention. In thisembodiment, a method for forming a dielectric film includes forming alayer of HfO₂ on a substrate in a reaction chamber by atomic layerdeposition using a HfI₄ precursor, and forming a layer of ZrO₂ on theHfO₂ layer by atomic layer deposition to form a HfO₂/ZrO₂ composite.Using the ALD process provides for the formation of the HfO₂/ZrO₂composite as a nanolaminate. An embodiment of this method can beimplemented with the atomic layer deposition system of FIG. 2A,B.

At block 405, a substrate is prepared. The substrate used for forming atransistor is typically a silicon or silicon containing material. Inother embodiments, germanium, gallium arsenide, silicon-on-sapphiresubstrates, or other suitable substrates may be used. This preparationprocess includes cleaning of the substrate 210 and forming layers andregions of the substrate, such as drains and sources of a metal oxidesemiconductor (MOS) transistor, prior to forming a gate dielectric. Thesequencing of the formation of the regions of the transistor beingprocessed follows typical sequencing that is generally performed in thefabrication of a MOS transistor as is well known to those skilled in theart. Included in the processing prior to forming a gate dielectric isthe masking of substrate regions to be protected during the gatedielectric formation, as is typically performed in MOS fabrication. Inthis embodiment, the unmasked region includes a body region of atransistor, however one skilled in the art will recognize that othersemiconductor device structures may utilize this process. Additionally,the substrate 210 in its ready for processing form is conveyed into aposition in reaction chamber 220 for ALD processing.

At block 410, a precursor containing hafnium is pulsed into reactionchamber 220. In particular, HfI₄ is used as a source material. The HfI₄is pulsed into reaction chamber 220 through the gas-distribution fixture240 onto substrate 210. The flow of the HfI₄ is controlled by mass-flowcontroller 256 from gas source 251. In one embodiment, the substratetemperature is maintained between about 225° C. and about 500° C. Inanother embodiment, the substrate temperature is maintained betweenabout 250° C. and about 325° C. The lower temperature allows for forminga dielectric film suited for use as a gate dielectric, since anamorphous layer tends to more readily form at lower processingtemperatures. The HfI₄ reacts with the surface of the substrate 210 inthe desired region defined by the unmasked areas of the substrate 210.

At block 415, a first purging gas is pulsed into the reaction chamber220. In particular, pure nitrogen with a purity greater than 99.99% isused as a purging gas for HfI₄. The nitrogen flow is controlled bymass-flow controller 266 from the purging gas source 261 into the gasconduit 270. Using the pure nitrogen purge avoids overlap of theprecursor pulses and possible gas phase reactions. A nitrogen gas canalso be used as a carrier gas for the precursors. Following the purge, afirst oxygen containing precursor is pulsed into the reaction chamber220, at block 420. For the hafnium sequence using HfI₄ as the precursor,water vapor is selected as the precursor acting as an oxidizing reactantto form a HfO₂ on the substrate 210. Alternately, a vapor solution ofH₂O—H₂O₂ can be used as the oxygen containing precursor. The water vaporis pulsed into the reaction chamber 220 through gas conduit 270 from gassource 252 by mass-flow controller 257. The water vapor aggressivelyreacts at the surface of substrate 210.

Following the pulsing of oxidizing reactant water vapor, the firstpurging gas is injected into the reaction chamber 220, at block 425. Inthe HfI₄/water vapor sequence, pure nitrogen gas is used to purge thereaction chamber after pulsing each precursor gas. Excess precursor gas,and reaction by-products are removed from the system by the purge gas inconjunction with the exhausting of the reaction chamber 220 using vacuumpump 282 through mass-flow controller 287, and exhausting of the gasconduit 270 by the vacuum pump 281 through mass-flow controller 286.

During the HfI₄/water vapor sequence, the substrate is held betweenabout 250° C. and about 325° C. by the heating element 230. In otherembodiments the substrate is held between about 225° C. and 500° C. TheHfI₄ pulse time ranges from about 1.0 sec to about 2.0 sec. After theHfI₄ pulse, the hafnium sequence continues with a purge pulse followedby a water vapor pulse followed by a purge pulse. In one embodiment,performing a purge pulse followed by a water vapor pulse followed by apurge pulse takes about 2 seconds. In another embodiment, each pulse inthe hafnium sequence has a 2 second pulse period. In another embodiment,the pulse periods for the precursors are 2 seconds, while the purge gaspulse period ranges from five second to twenty seconds.

At block 430, a determination is made as to whether a desired thicknessof the HfO₂ layer has been formed. The thickness of a HfO₂ film afterone cycle is determined by a fixed growth rate for the pulsing periodsand precursors used in the hafnium sequence, set at a value such as Nnm/cycle. For a desired HfO₂ film thickness, t, in an application suchas forming a gate dielectric of a MOS transistor, the ALD process shouldbe repeated for t/N cycles. The desired thickness should be attainedafter t/N cycles. If less than t/N cycles have been completed, theprocess starts over at block 410 with the pulsing of the precursorcontaining hafnium, which in the embodiment discussed above is a HfI₄gas. If t/N cycles have completed, no further ALD processing of HfO₂ isrequired and the HfO₂ layer is ready to be formed as a composite with aZrO₂ layer.

At block 435, a precursor containing zirconium is pulsed into thereaction chamber 220. In one embodiment, ZrI₄ is used as the zirconiumcontaining precursor. In another embodiment, ZrCl₄ is used as thezirconium containing precursor. The ZrI₄ is evaporated from acontainment area held at about 250° C. in gas source 253. It is pulsedto the surface of the substrate 210 through gas-distribution fixture 240from gas source 253 by mass-flow controller 258. The ZrI₄ is introducedonto the HfO₂ layer that was formed during the HfI₄/water vaporsequence.

At block 440, a second purging gas is introduced into the system. For aZrI₄ precursor, nitrogen gas is used as a purging and carrier gas. Thenitrogen flow is controlled by mass-flow controller 267 from the purginggas source 262 into the gas conduit 270 and subsequently into thereaction chamber 220. Following the nitrogen purge, at block 445, asecond oxygen containing precursor is pulsed into the reaction chamber220. For the zirconium sequence using ZrI₄ as the precursor, a vaporsolution of H₂O—H₂O₂ is selected as the precursor acting as an oxidizingreactant to interact with the zirconium deposited on the HfO₂ layer onthe substrate 210. The H₂O—H₂O₂ vapor solution is pulsed into thereaction chamber 220 through gas conduit 270 from gas source 254, heldat about room temperature, by mass-flow controller 259. The H₂O—H₂O₂vapor solution aggressively reacts at the surface of substrate 210 toform a ZrO₂ layer.

Following the pulsing of the H₂O—H₂O₂ vapor solution acting as anoxidizing reactant, the nitrogen purging gas is injected into thereaction chamber 200, at block 450. In the ZrI₄/H₂O—H₂O₂ vapor solutionsequence, nitrogen gas is used to purge the reaction chamber afterpulsing each precursor gas. In another embodiment, argon gas is used asthe purging gas. Excess precursor gas, and reaction by-products areremoved from the system by the purge gas in conjunction with theexhausting of the reaction chamber 220 using vacuum pump 282 throughmass-flow controller 287, and exhausting of the gas conduit 270 by thevacuum pump 281 through mass-flow controller 286.

During the ZrI₄/H₂O—H₂O₂ vapor solution sequence, the substrate is heldbetween about 250° C. and about 325° C. by the heating element 230. Inother embodiments, the substrate is held between about 275° C. and about500° C. In one embodiment, the process pressure is maintained at about250 Pa during the zirconium sequence. Pulse times for the ZrI₄ and theH₂O—H₂O₂ vapor solution were about 2 sec for both precursors, withpurging pulse times of about 2 secs.

At 455, similar to the HfO₂ layer formation, a determination is made asto whether the ZrO₂ layer has the desired thickness by determining if adesired number of zirconium cycles have been performed. If the number ofzirconium cycles performed is less than the number needed to form thedesired thickness, the zirconium containing precursor is pulsed into thereaction chamber, at block 435, and the process continues. If thedesired number of zirconium cycles has been performed, this completesnot only the ZrI₄/H₂O—H₂O₂ vapor solution sequence, but it alsocompletes a hafnium sequence/zirconium sequence cycle forming aHfO₂/ZrO₂ nanolaminate.

Upon completing the formation of the HfO₂/ZrO₂ nanolaminate, thenanolaminate can be annealed. The annealing can be performed at atemperature between about 300° C. and about 800° C. in an inert ornitrogen atmosphere.

At block 460, after forming the HfO₂/ZrO₂ nanolaminate, processing thedevice containing the HfO₂/ZrO₂ nanolaminate is completed. In oneembodiment, completing the device includes completing the formation of atransistor. Alternately, completing the process includes completing theconstruction of a memory device having a array with access transistorsformed with gate dielectrics containing HfO₂/ZrO₂ nanolaminates.Further, in another embodiment, completing the process includes theformation of an electronic system including an information handlingdevice that uses electronic devices with transistors formed with gatedielectrics containing HfO₂/ZrO₂ nanolaminates. Typically, informationhandling devices such as computers include many memory devices, havingmany access transistors.

In one embodiment, a HfO₂/ZrO₂ nanolaminate includes one HfO₂ layer andone HfO₂/ZrO₂ layer. The completed HfO₂/ZrO₂ nanolaminate has athickness in which the thickness of the HfO₂ layer is about one-half thethickness of the completed HfO₂/ZrO₂ nanolaminate. In anotherembodiment, a completed HfO₂/ZrO₂ nanolaminate includes multiplealternating layers of HfO₂ and ZrO₂, which requires that at block 455,once a given ZrO₂ layer has been formed with a desired thickness, ahafnium sequence is then started at block 410. This process, proceedingfrom completing the zirconium sequence at block 455 to starting thehafnium sequence at block 410, continues until the desired number ofalternating layers of HfO₂ and ZrO₂ have been formed. The HfO₂/ZrO₂nanolaminate formation begins with forming a HfO₂ layer, but may endwith forming ZrO₂ layer or a HfO₂ layer. ALD provides for theengineering of a HfO₂/ZrO₂ nanolaminate. For example, nanolaminates canbe formed with n number of HfO₂/ZrO₂ composite layers where the HfO₂layer is formed with x number of hafnium cycles and y number ofzirconium cycles. Alternately, nanolaminates can be formed with n numberof HfO₂/ZrO₂ composite layers where the first composite layer has a HfO₂layer formed with x₁ number of hafnium cycles and y₁ number of zirconiumcycles, a second composite layer has a HfO₂ layer formed with x₂ numberof hafnium cycles and y₂ number of zirconium cycles, extended to then^(th) composite layer having a HfO₂ layer formed with x_(n) number ofhafnium cycles and y_(n) number of zirconium cycles. Such tailoring ofthe HfO₂/ZrO₂ nanolaminate provides for forming dielectric films with adesigned physical thickness, t, and equivalent oxide thickness, t_(eq).

In the hafnium sequence and in the zirconium sequence, pulsing eachprecursor into the reaction chamber is controlled for a predeterminedperiod, the predetermined period being individually controlled for eachprecursor pulsed into the reaction chamber. Additionally, the substrateis maintained at a selected temperature for forming each layer, wherethe selected temperature set independently for forming each layer.

In a recent article by O. Sneh et al., Thin Solid Films, vol. 402, pp.248-261 (2002), atomic layer deposition of thin films was discussed. Thearticle noted that the growth rate for HfO₂ is, typically, about 0.8Å/cycle. Similarly, in a recent article by K. Kukli et al., Journal ofthe Electrochemical Society, vol. 148, no. 12, pp. F227-F232 (2001),dealing with ZrO₂ formed by ALD using ZrI₄, it was noted that at about agrowth temperature of about 300° C., ZrO₂ growth rate was about 0.075nm/cycle. Thus, in the embodiments for forming HfO₂/ZrO₂ nanolaminatesusing ALD for all composite layers, each material layer can be grown atabout 0.75-0.80 Å/cycle.

FIG. 5 illustrates a flow diagram of elements for an embodiment of amethod to process a nanolaminate of HfO₂/ZrO₂ using atomic layerdeposition and thermal evaporation/plasma oxidation, according to theteachings of the present invention. In one embodiment, a nanolaminate ofHfO₂/ZrO₂ is formed by a method that includes forming a layer of hafniumoxide on a substrate in a reaction chamber by atomic layer depositionusing a HfI₄ precursor, at block 505, forming a layer of zirconium onthe layer of hafnium oxide by thermal evaporation, at block 510, andoxidizing the zirconium layer using a krypton(Kr)/oxygen(O₂) mixedplasma to form a HfO₂/ZrO₂ composite, at block 515. The HfO₂/ZrO₂composite is a nanolaminate, whose thickness can be controlled byprecisely controlling the ALD formation of HfO₂, and thermal depositionof zirconium. In one embodiment, the thermal evaporation of zirconium isperformed using electron beam evaporation.

FIG. 6 shows an embodiment of an electron beam evaporation process forforming a layer of zirconium on a layer of HfO₂ to process ananolaminate of HfO₂/ZrO₂, according to the teachings of the presentinvention. In the embodiment of FIG. 6, a substrate 610 is locatedinside a deposition chamber 660. The substrate in this embodiment ismasked by a first masking structure 670 and a second masking structure671. In this embodiment, the unmasked region 633 includes a body regionof a transistor on which a layer of HfO₂ is formed. However one skilledin the art will recognize that other semiconductor device structures mayutilize this process. Also located within the deposition chamber 660 isan electron gun 663 and a target 661. The electron gun 663 provides anelectron beam 664 directed at target 661 containing a source materialfor forming ZrO₂ on the unmasked region HfO₂ layer 633 of the substrate610. The electron gun 663 includes a rate monitor for controlling therate of evaporation of the material in the target 661 at which theelectron beam 664 is directed. For convenience, control displays andnecessary electrical connections as are known to those skilled in theart are not shown in FIG. 6.

During the evaporation process, the electron gun 663 generates anelectron beam 664 that hits target 661. In one embodiment, target 661contains a zirconium metal source, which is evaporated due to the impactof the electron beam 664. The evaporated material 668 is thendistributed throughout the chamber 660. A layer of zirconium is grownforming a film 640 on the surface of the HfO₂ layer 633 on substrate610, which is maintained at a temperature between 150° C. and 200° C.The growth rate can vary with a typical rate of 0.1 Å/s. Afterdepositing a zirconium layer on the HfO₂ layer 633, the zirconium layeris oxidized.

The evaporation chamber 660 can be included as part of an overallprocessing system including ALD system 200 of FIG. 2. To avoidcontamination of the surface of the HfO₂ layer 633, evaporation chamber660 can be connected to ALD system 200 using sealable connections tomaintain the substrate, which is substrate 210 in FIG. 2 and substrate610 of FIG. 6, in an appropriate environment between ALD processing ofthe HfO₂ layer and Zr evaporation. Other means as are known to thoseskilled in the art can be employed for maintaining an appropriateenvironment between different processing procedures.

FIGS. 7A-7C show a low temperature oxidation process that is used in oneembodiment to form a layer of ZrO₂ on a layer of HfO₂. FIG. 7A shows anembodiment of a zirconium layer 720 deposited on a HfO₂ layer 710,according to the teachings of the present invention. The HfO₂ layer 710is formed on substrate 700 using an ALD process, as previouslydiscussed, having an substrate interface 730. The Zr layer 720 isdeposited on the HfO₂ layer 710 by electron beam evaporation, asdiscussed above, forming an interface 740 with the HfO₂ layer 710 andhaving an outer surface 750. The combined film with the Zr layer 720deposited on the HfO₂ layer 710 has a total thickness 752. The layers710, 720 are deposited over a body region of a transistor, however thelayers may be deposited on any surface within the scope of theinvention.

FIG. 7B shows an embodiment of a partially oxidized zirconium layer 770deposited on a HfO₂ layer 710, according to the teachings of the presentinvention. In FIG. 7B, the layer 720 is in the process of beingoxidized. In one embodiment, the oxidation process includes akrypton/oxygen mixed plasma oxidation process. The mixed plasma processgenerates atomic oxygen or oxygen radicals in contrast to molecularoxygen or O₂ used in conventional thermal oxidation. The atomic oxygenis introduced to the layer from all exposed directions as indicated byarrows 760, creating an oxide portion 770. The atomic oxygen continuesto react with the layer and creates an oxidation interface 742. As thereaction progresses, atomic oxygen diffuses through the oxide portion770 and reacts at the oxidation interface 742 until the layer iscompletely converted to an oxide of the deposited material layer.

FIG. 7C shows an embodiment of a ZrO₂ substantially completely oxidizedand formed on a layer of HfO₂ to form a nanolaminate of HfO₂/ZrO₂,according to the teachings of the present invention. FIG. 7C shows theresulting oxide layer 770 which spans a physical thickness 772 from theouter surface 750 to the interface 740. The overall thickness 752 of theHfO₂/ZrO₂ composite in FIG. 7C has increased from that of the Zr layerdeposited on the HfO₂ layer in FIG. 7A, due to the oxidation of thezirconium.

In an embodiment, the processing variables for the mixed plasmaoxidation include a low ion bombardment energy of less than 7 eV, a highplasma density above 10¹²/cm³ and a low electron temperature below 1.3eV. In another embodiment, the substrate temperature is approximately400° C. In another embodiment, a mixed gas of 3% oxygen with the balancebeing krypton at a pressure of 1 Torr is used. In one embodiment, amicrowave power density of 5 W/cm² is used. The oxidation processprovides a growth rate of 1.5 nm/min.

The low temperature mixed plasma oxidation process described aboveallows the deposited layer to be oxidized at a low temperature. Themixed plasma process in one embodiment is performed at approximately400° C. in contrast to prior thermal oxidation processes that areperformed at approximately 1000° C.

FIG. 8 illustrates a flow diagram of elements for an embodiment of amethod to process a nanolaminate of HfO₂/ZrO₂ using atomic layerdeposition and chemical vapor deposition (CVD), according to theteachings of the present invention. This embodiment of the methodincludes forming a layer of hafnium oxide on a substrate in a reactionchamber by atomic layer deposition using a HfI₄ precursor, at block 805,and forming a layer of zirconium oxide on the layer of hafnium oxide bychemical vapor deposition to form a HfO₂/ZrO₂ composite, at block 810.The HfO₂ layer is formed by ALD as discussed in the embodiments above.In one embodiment, the ZrO₂ layer is formed by rapid thermal CVD atabout 500° C. Subsequently, a nitrogen anneal is performed between about700° C. and about 800° C. for about 30 sec. A rapid thermal CVD system,as is known to those skilled in the art, is used to form the ZrO₂ layer.

FIG. 9 illustrates a flow diagram of elements for an embodiment of amethod to process a nanolaminate of HfO₂/ZrO₂ using atomic layerdeposition and pulsed-laser deposition, according to the teachings ofthe present invention. This embodiment of the method includes forming alayer of hafnium oxide on a substrate in a reaction chamber by atomiclayer deposition using a HfI₄ precursor, at block 905, and forming alayer of zirconium oxide on the layer of hafnium oxide by pulsed-laserdeposition to form a HfO₂/ZrO₂ composite, at block 910. The HfO₂ layeris formed by ALD as discussed in the embodiments above. A pulsed-laserdeposition system is similar to the electron beam evaporation system 660of FIG. 6 with the electron gun 663 replaced by a laser and focusingoptics, though the laser and focusing optics need not be located in theevaporation reaction chamber. A beam from the laser is focused on atarget, which causes an ablation of material from the target. Thematerial removed from the target deposits on an unmasked HfO₂ layerlocated on a substrate. Controlling the focusing of the beam from thelaser on the source target provides for precision growth rate of theZrO₂ layer.

In one embodiment, a substrate temperature is maintained between about200° C. to about 800° C. during pulsed-laser deposition. A beam from alaser source such as a excimer laser is focused on a rotating zirconiumtarget source in a deposition chamber with an O₂ pressure of about 0.2Torr to form a ZrO₂ layer on a HfO₂ layer. Other laser sources andconfigurations can be used as is known by those skilled in the art.

FIG. 10 illustrates a flow diagram of elements for an embodiment of amethod to process a nanolaminate of HfO₂/ZrO₂ using atomic layerdeposition and jet-vapor deposition, according to the teachings of thepresent invention. This embodiment of the method includes forming alayer of hafnium oxide on a substrate in a reaction chamber by atomiclayer deposition using a HfI₄ precursor, at block 1005, and forming alayer of zirconium oxide on the layer of hafnium oxide by jet-vapordeposition to form a HfO₂/ZrO₂ composite, at block 1010. The HfO₂ layeris formed by ALD as discussed in the embodiments above. The ZrO₂ layercan be formed using jet-vapor deposition techniques as is known to thoseskilled in the art.

In one embodiment, the jet-vapor deposition zirconium and oxygen vaporsare directed to the HfO₂ layer out of source nozzles by supersonic Arjets. Using jet-vapor deposition in a low pressure atmosphere allows forforming the ZrO₂ layer at at room temperature. In one embodiment,annealing is performed subsequent to forming the ZrO₂ layer at a about800° C. In one embodiment, the annealing is performed using a nitrogenrapid thermal annealing (RTA). The annealing can be performed after eachZrO₂ layer is formed in the composite of alternating layers of theHfO₂/ZrO₂ nanolaminate and/or at the completion of the HfO₂/ZrO₂nanolaminate.

In each of the various embodiments for forming ZrO₂ layers, theHfO₂/ZrO₂ nanolaminates can be annealed in a temperature range frombetween 300° C. to 800 ° C. Typically the annealing is for a short timeand in performed in a nitrogen atmosphere or in some other inertatmosphere.

Bulk layers of HfO₂ and bulk layers of ZrO₂ both have a dielectricconstant of about 25. Consequently, a material film composed of bulklayers of HfO₂ and ZrO₂ will also have a dielectric constant of about25. However, thin layers of a material, typically, have dielectricconstants somewhat less than their bulk counterparts. The reduced valueof the dielectric constants for ultra thin material films is due in partto the formation of an interfacial layer between the material film andthe substrate. Some materials formed on silicon substrates form a SiO₂interfacial layer, while other materials form an silicide interfaciallayer. The material silicide in many cases will have a dielectricgreater than SiO₂, but less than the bulk material dielectric constant.ZrO₂ formed on silicon substrates may result in an interfacial regionwhere silicon diffuses through a layer of ZrO₂ to form apoly-silicon/ZrO₂/silicon interfacial region, as reported by C. H. Leeet al., IEDM 2000, 27-30 (2000). Further, nanolaminates of ZrO₂/HfO₂were reported to have SiO₂ interfacial layer when formed by ALD usingZrCl₄ and HfCl₄ precursors. See H. Zhang et al., Journal of theElectrochemical Society, vol. 148, no. 4, pp. F63-F66 (2001). Toeliminate the SiO₂ interfacial layer, Zhang et al. grew ZrO₂/HfO₂nanolaminates on nitrated Si substrates producing dielectric constantsranging from 9 to 14 with low leakage currents ranging from 2.2×10⁻⁶ to1.2×10⁻⁸ A/cm³ at 1 MV/cm.

In the various embodiments according to the teachings of the presentinvention, HfO₂/ZrO₂ nanolaminates are formed by ALD of HfO₂ onsubstrates using a HfI₄ precursor. Subsequently, a layer of ZrO₂ isformed on the HfO₂ layer by various deposition techniques. TheseHfO₂/ZrO₂ nanolaminates form a stable interface with a siliconsubstrate. Using ALD, the size and effect of interfacial layer betweenthe silicon substrate and the first HfO₂ layer will depend on thereactivity of the HfO₂ in forming an abrupt transition from siliconsurface to HfO₂ layer. Consequently, dielectric films containingHfO₂/ZrO₂ nanolaminates can have dielectric constants ranging from 9 or10 to 25. Additionally, forming the HfO₂ layer at relatively lowtemperatures provides a means for enabling the formation of HfO₂/ZrO₂nanolaminates that are amorphous.

Another factor setting a lower limit for the scaling of a dielectriclayer is the number of monolayers of the dielectric structure necessaryto develop a full band gap such that good insulation is maintainedbetween an underlying silicon layer and an overlying conductive layer onthe dielectric layer or film. This requirement is necessary to avoidpossible short circuit effects between the underlying silicon layer andthe overlying conductive layer used. In one embodiment, for several HfO₂monolayers and several ZrO₂ monolayers forming a nanolaminate, anexpected lower limit for the physical thickness of a dielectric layergrown by forming HfO₂/ZrO₂ nanolaminates is anticipated to be in aboutthe 2-4 nm range. Consequently, typical dielectric layers or films canbe grown by forming HfO₂/ZrO₂ nanolaminates having physical thickness inthe range of 4 to 10 nm. HfO₂ used as the initial layer is expected toprovide excellent overall results with respect to reliability, currentleakage, and ultra-thin t_(eq). Further, using ALD for processing alllayers of a HfO₂/ZrO₂ nanolaminate, the transitions between such oxidelayers can be engineered to be abrupt or graded. Thus, the number oflayers used, the thickness of each layer, and the nature of theinterface between each layer can be engineered to provide the desiredelectrical characteristics.

With HfO₂ layers formed by ALD and ZrO₂ layers formed according to oneof the various embodiments described herein, HfO₂/ZrO₂ nanolaminates canhave a wide range of thicknesses and dielectric constants. The physicalthicknesses can range from about 2 nm to about 10 nm with typicalthickness ranging from about 4 nm to about 10 nm. Such layers have aneffective dielectric constant ranging from 9 or 10 to 25. The expectedt_(eq) ranges for various effective dielectric constants are shown inthe following: Physical Thickness Physical Thickness Physical Thicknesst = 0.5 nm (5 Å) t = 1.0 nm (10 Å) t = 5.0 nm (50 Å) κ t_(eq) (Å) t_(eq)(Å) t_(eq) (Å) 9 2.17 4.33 21.67 17 1.15 2.29 11.47 21 .93 1.86 9.29 25.78 1.56 7.8

As mentioned, the lower limit on the scaling of a layer containingHfO₂/ZrO₂ nanolaminates depends on the monolayers of the film necessaryto develop a full band gap such that good insulation is maintainedbetween an underlying silicon layer and an overlying conductive layer tothe HfO₂/ZrO₂ nanolaminate film. From above, it is apparent that a filmcontaining HfO₂/ZrO₂ nanolaminates can be attained with a t_(eq) rangingfrom 3 Å to 12 Å. Further, a dielectric film with completely formed bandstructures and monolayer formations can provide a t_(eq) significantlyless than 2 or 3 Å.

The novel process described above provides significant advantages byperforming atomic layer deposition of HfO₂ZrO₂ in a hafnium sequenceusing HfI₄ precursors followed by the formation of a ZrO₂ layer on theHfO₂ layer. Further, by independently controlling the various parametersfor each sequence a gate dielectric with a selected dielectric constantcan be formed. Additionally, the novel process can be implemented toform transistors, memory devices, and information handling devices. Withcareful preparation and engineering of the HfO₂/ZrO₂ nanolaminateslimiting the size of interfacial regions, a t_(eq) down to 2.5 Å orlower is anticipated.

A transistor 100 as depicted in FIG. 1 can be formed by forming asource/drain region 120 and another source/drain region 130 in a siliconbased substrate 110 where the two source/drain regions 120, 130 areseparated by a body region 132. The body region 132 separated by thesource/drain 120 and the source/drain 130 defines a channel having achannel length 134. A dielectric film is formed on the substrate 110 byforming a layer of hafnium oxide on substrate 110 in a reaction chamberby atomic layer deposition using a HfI₄ precursor and forming a layer ofzirconium oxide on the layer of hafnium oxide to form a HfO₂/ZrO₂composite. The resulting HfO₂/ZrO₂ composite is a nanolaminate. TheseHfO₂/ZrO₂ nanolaminates can be formed using any of the variousembodiments previously discussed. These HfO₂/ZrO₂ nanolaminates arecontained in a dielectric film defining the gate dielectric 140.

A gate is formed over the gate dielectric 140. Typically, forming thegate includes forming a polysilicon layer, though a metal gate can beformed in an alternative process. Forming the substrate, source/regionregions, and the gate is performed using standard processes known tothose skilled in the art. Additionally, the sequencing of the variouselements of the process for forming a transistor is conducted withstandard fabrication processes, also as known to those skilled in theart.

Embodiments of the method of forming HfO₂/ZrO₂ nanolaminates as a gatedielectric can be applied to other transistor structures havingdielectric layers. For example, FIG. 11 shows an embodiment of aconfiguration of a transistor capable of being fabricated, according tothe teachings of the present invention. The transistor 1100 includes asilicon based substrate 1110 with two source/drain regions 1120, 1130separated by a body region 1132. The body region 1132 between the twosource/drain regions 1120, 1130 defines a channel region having achannel length 1134. Located above the body region 1132 is a stack 1155including a gate dielectric 1140, a floating gate 1152, a floating gatedielectric 1142, and control gate 1150. The gate dielectric 1140containing HfO₂/ZrO₂ nanolaminates is formed according to the teachingsof the present invention as described above with the remaining elementsof the transistor 1100 formed using processes known to those skilled inthe art. Alternately, both the gate dielectric 1140 and the floatinggate dielectric 1142 can be formed containing HfO₂/ZrO₂ nanolaminates,in accordance with the present invention as described above.

Transistors created by the methods described above may be implementedinto memory devices and electronic systems including informationhandling devices. Information handling devices having a dielectric layercontaining HfO₂/ZrO₂ nanolaminates can be constructed using variousembodiments of the methods described above. Such information devices caninclude wireless systems, telecommunication systems, and computers. Anembodiment of a computer having a dielectric layer containing HfO₂/ZrO₂nanolaminates is shown in FIGS. 12-14 and described below. Whilespecific types of memory devices and computing devices are shown below,it will be recognized by one skilled in the art that several types ofmemory devices and electronic systems including information handlingdevices utilize the invention.

FIG. 12 shows an embodiment of a personal computer 1200 incorporatingdevices, according to the teachings of the present invention. Personalcomputer 1200 includes a monitor 1201, keyboard input 1202 and a centralprocessing unit 1204.

FIG. 13 illustrates a schematic view of an embodiment of a centralprocessing unit 1204 incorporating devices, according to the teachingsof the present invention. The central processing unit 1204 typicallyincludes microprocessor 1306, memory bus circuit 1308 having a pluralityof memory slots 1312(a-n), and other peripheral circuitry 1310.Peripheral circuitry 1310 permits various peripheral devices 1324 tointerface processor-memory bus 1320 over input/output (I/O) bus 1322.The personal computer 1200 shown in FIGS. 12 and 13 also includes atleast one transistor having a gate dielectric containing HfO₂/ZrO₂nanolaminates in an embodiment according to the teachings of the presentinvention.

Microprocessor 1306 produces control and address signals to control theexchange of data between memory bus circuit 1308 and microprocessor 1306and between memory bus circuit 1308 and peripheral circuitry 1310. Thisexchange of data is accomplished over high speed memory bus 1320 andover high speed I/O bus 1322.

Coupled to memory bus 1320 are a plurality of memory slots 1312(a-n)which receive memory devices well known to those skilled in the art. Forexample, single in-line memory modules (SIMMs) and dual in-line memorymodules (DIMMs) may be used in the implementation of the presentinvention.

These memory devices can be produced in a variety of designs whichprovide different methods of reading from and writing to the dynamicmemory cells of memory slots 1312. One such method is the page modeoperation. Page mode operations in a DRAM are defined by the method ofaccessing a row of a memory cell arrays and randomly accessing differentcolumns of the array. Data stored at the row and column intersection canbe read and output while that column is accessed. Page mode DRAMsrequire access steps which limit the communication speed of memorycircuit 1308.

An alternate type of device is the extended data output (EDO) memorywhich allows data stored at a memory array address to be available asoutput after the addressed column has been closed. This memory canincrease some communication speeds by allowing shorter access signalswithout reducing the time in which memory output data is available onmemory bus 1320. Other alternative types of devices include SDRAM, DDRSDRAM, SLDRAM and Direct RDRAM as well as others such as SRAM or Flashmemories.

FIG. 14 illustrates a schematic view of an embodiment of a DRAM memorydevice 1400 according to the teachings of the present invention. DRAMdevice 1400 is compatible with memory slots 1312(a-n). The descriptionof DRAM 1400 has been simplified for purposes of illustrating a DRAMmemory device and is not intended to be a complete description of allthe features of a DRAM. Those skilled in the art will recognize that awide variety of memory devices may be used in the implementation of thepresent invention. The example of a DRAM memory device shown in FIG. 14includes at least one transistor having a gate dielectric containingHfO₂/ZrO₂ nanolaminates in an embodiment according to the teachings ofthe present invention.

Control, address and data information provided over memory bus 1320 isfurther represented by individual inputs to DRAM 1400, as shown in FIG.14. These individual representations are illustrated by data lines 1402,address lines 1404 and various discrete lines directed to control logic1406.

As is well known in the art, DRAM 1400 includes memory array 1410 whichin turn comprises rows and columns of addressable memory cells. Eachmemory cell in a row is coupled to a common word line. The word line iscoupled to gates of individual transistors, where at least onetransistor has a gate coupled to a gate dielectric containing HfO₂/ZrO₂nanolaminates in accordance with the method and structure previouslydescribed above. Additionally, each memory cell in a column is coupledto a common bit line. Each cell in memory array 1410 includes a storagecapacitor and an access transistor as is conventional in the art.

DRAM 1400 interfaces with, for example, microprocessor 1306 throughaddress lines 1404 and data lines 1402. Alternatively, DRAM 1400 mayinterface with a DRAM controller, a micro-controller, a chip set orother electronic system. Microprocessor 1306 also provides a number ofcontrol signals to DRAM 1400, including but not limited to, row andcolumn address strobe signals RAS and CAS, write enable signal WE, anoutput enable signal OE and other conventional control signals.

Row address buffer 1412 and row decoder 1414 receive and decode rowaddresses from row address signals provided on address lines 1404 bymicroprocessor 1306. Each unique row address corresponds to a row ofcells in memory array 1410. Row decoder 1414 includes a word linedriver, an address decoder tree, and circuitry which translates a givenrow address received from row address buffers 1412 and selectivelyactivates the appropriate word line of memory array 1410 via the wordline drivers.

Column address buffer 1416 and column decoder 1418 receive and decodecolumn address signals provided on address lines 1404. Column decoder1418 also determines when a column is defective and the address of areplacement column. Column decoder 1418 is coupled to sense amplifiers1420. Sense amplifiers 1420 are coupled to complementary pairs of bitlines of memory array 1410.

Sense amplifiers 1420 are coupled to data-in buffers 1422 and data-outbuffers 1424. Data-in buffers 1422 and data-out buffers 1424 are coupledto data lines 1402. During a write operation, data lines 1402 providedata to data-in buffers 1422. Sense amplifier 1420 receives data fromdata-in buffers 1422 and stores the data in memory array 1410 as acharge on a capacitor of a cell at an address specified on address lines1404.

During a read operation, DRAM 1400 transfers data to microprocessor 1306from memory array 1410. Complementary bit lines for the accessed cellare equilibrated during a precharge operation to a reference voltageprovided by an equilibration circuit and a reference voltage supply. Thecharge stored in the accessed cell is then shared with the associatedbit lines. A sense amplifier of sense amplifiers 1420 detects andamplifies a difference in voltage between the complementary bit lines.The sense amplifier passes the amplified voltage to data-out buffers1424.

Control logic 1406 is used to control the many available functions ofDRAM 1400. In addition, various control circuits and signals notdetailed herein initiate and synchronize DRAM 1400 operation as known tothose skilled in the art. As stated above, the description of DRAM 1400has been simplified for purposes of illustrating the present inventionand is not intended to be a complete description of all the features ofa DRAM. Those skilled in the art will recognize that a wide variety ofmemory devices, including but not limited to, SDRAMs, SLDRAMs, RDRAMsand other DRAMs and SRAMs, VRAMs and EEPROMs, may be used in theimplementation of the present invention. The DRAM implementationdescribed herein is illustrative only and not intended to be exclusiveor limiting.

CONCLUSION

A gate dielectric containing HfO₂/ZrO₂ nanolaminates and a method offabricating such a gate produces a reliable gate dielectric having anequivalent oxide thickness thinner than attainable using SiO₂. Gatedielectrics containing HfO₂/ZrO₂ nanolaminates formed using the methodsdescribed herein are thermodynamically stable such that the gatedielectrics formed will have minimal reactions with a silicon substrateor other structures during processing.

Transistors, higher level ICs or devices, and systems are constructedutilizing the novel process for forming a gate dielectric having anultra thin equivalent oxide thickness, t_(eq). Gate dielectric layers orfilms containing HfO₂/ZrO₂ nanolaminates are formed having a highdielectric constant (κ), where the gate dielectrics are capable of at_(eq) thinner than 10 Å, thinner than the expected limit for SiO₂ gatedielectrics. At the same time, the physical thickness of the HfO₂/ZrO₂nanolaminates is much larger than the SiO₂ thickness associated with thet_(eq) limit of SiO₂. Forming the larger thickness provides advantagesin processing the gate dielectric. Further, HfO₂/ZrO₂ nanolaminatesprocessed in relatively low temperatures can provide amorphousdielectric films having relatively low leakage current for use asdielectric layers in electronic devices and systems.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. It is to be understood that the above description is intendedto be illustrative, and not restrictive. Combinations of the aboveembodiments, and other embodiments will be apparent to those of skill inthe art upon reviewing the above description. The scope of the inventionincludes any other applications in which the above structures andfabrication methods are used. The scope of the invention should bedetermined with reference to the appended claims, along with the fullscope of equivalents to which such claims are entitled.

1. A method comprising: forming a layer of hafnium oxide by atomic layerdeposition using a HfI₄ precursor; forming a layer of zirconium oxide onthe layer of hafnium oxide to form a nanolaminate having a hafnium oxidelayer and a zirconium oxide layer, wherein the layer of zirconium oxideis formed by a process other than atomic layer deposition.
 2. The methodof claim 1, wherein the method includes forming the layer of hafniumoxide as an initial layer of the nano laminate and forming another layerof hafnium oxide as the final layer of the nanolaminate.
 3. The methodof claim 1, wherein the layer of zirconium oxide is formed by one ormore of thermal evaporation, chemical vapor deposition, pulsed-laserdeposition, or jet-vapor deposition.
 4. The method of claim 1, whereinthe method includes forming the nanolaminate as a gate dielectric in atransistor.
 5. The method of claim 1, wherein the method includesforming the nanolaminate as a floating gate dielectric in a transistor.6. The method of claim 1, wherein the method includes forming the nanolaminate as a dielectric in a transistor of a memory array in a memorydevice.
 7. The method of claim 6, wherein the method includes providinga bus to couple the memory device to a processor in an electronicsystem.
 8. A method comprising: forming a dielectric film on asubstrate, the dielectric layer having a HfO₂/ZrO₂ nanolaminate, theHfO₂/ZrO₂ nanolaminate fabricated by forming a layer of hafnium oxide byatomic layer deposition using a HfI₄ precursor; forming a layer ofzirconium on the layer of hafnium oxide by thermal evaporation; andoxidizing the zirconium layer using a krypton(Kr)/oxygen(O₂) mixedplasma to form a layer of zirconium oxide.
 9. The method of claim 8,wherein the method includes forming the layer of hafnium oxide as aninitial layer of the nanolaminate on the substrate and forming anotherlayer of hafnium oxide as the final layer of the nanolaminate.
 10. Themethod of claim 8, wherein forming a layer of zirconium includes formingthe zirconium layer by electron beam evaporation, maintaining thesubstrate temperature between about 150° C. to about 200° C.
 11. Themethod of claim 8, wherein oxidizing the zirconium layer includes usingthe krypton(Kr)/oxygen(O₂) mixed plasma at about 400° C.
 12. The methodof claim 11, wherein using a krypton(Kr)/oxygen(O₂) mixed plasmaincludes an ion bombardment of less than about 7 eV, a plasma densityabove about 10¹²/cm³, and an electron temperature below about 1.3 eV.13. A method comprising: forming a dielectric film on a substrate, thedielectric layer having a HfO₂/ZrO₂ nanolaminate, the HfO₂/ZrO₂nanolaminate fabricated by forming a layer of hafnium oxide on thesubstrate in a reaction chamber by atomic layer deposition using a HfI₄precursor; and forming a layer of zirconium oxide on the layer ofhafnium oxide by chemical vapor deposition.
 14. The method of claim 13,wherein the method includes forming the layer of hafnium oxide as aninitial layer of the nanolaminate on the substrate and forming anotherlayer of hafnium oxide as the final layer of the nanolaminate.
 15. Themethod of claim 13, wherein forming a layer of zirconium oxide includesforming a layer of zirconium oxide by rapid thermal chemical vapordeposition at about 500° C.
 16. The method of claim 13, wherein themethod further includes a nitrogen anneal between about 700° C. andabout 900° C., after forming the layer of zirconium oxide.
 17. Themethod of claim 13, wherein forming a layer of hafnium oxide on asubstrate by atomic layer deposition using a HfI₄ precursor includespulsing a first oxygen containing precursor into the reaction chamberafter pulsing the HfI₄ precursor into the reaction chamber.
 18. Themethod of claim 17, wherein pulsing a first oxygen containing precursorincludes pulsing water vapor.
 19. A method comprising: forming adielectric film on a substrate, the dielectric layer having a HfO₂/ZrO₂nanolaminate, the HfO₂/ZrO₂ nanolaminate fabricated by: forming a layerof hafnium oxide on the substrate in a reaction chamber by atomic layerdeposition using a HfI₄ precursor; forming a layer of zirconium oxide onthe layer of hafnium oxide by pulsed-laser deposition.
 20. The method ofclaim 19, wherein the method includes forming the layer of hafnium oxideas an initial layer of the nanolaminate and forming another layer ofhafnium oxide as the final layer of the nanolaminate.
 21. The method ofclaim 19, wherein forming a layer of zirconium oxide includes forming alayer of zirconium oxide by pulsed-laser deposition with a substratetemperature between about 200° C. to about 800° C.
 22. The method ofclaim 19, wherein forming a layer of zirconium oxide includes forming alayer of zirconium oxide by pulsed-laser deposition with an O₂ pressureof about 0.2 Torr.
 23. The method of claim 19, wherein forming a layerof hafnium oxide on a substrate by atomic layer deposition using a HfI₄precursor includes pulsing a first oxygen containing precursor into thereaction chamber after pulsing the HfI₄ precursor into the reactionchamber.
 24. The method of claim 23, wherein pulsing a first oxygencontaining precursor includes pulsing a vapor solution of H₂O—H₂O₂. 25.A method comprising: forming a dielectric film on a substrate, thedielectric layer having a HfO₂/ZrO₂ nanolaminate, the HfO₂/ZrO₂nanolaminate fabricated by: forming a layer of hafnium oxide on thesubstrate in a reaction chamber by atomic layer deposition using a HfI₄precursor; and forming a layer of zirconium oxide on the layer ofhafnium oxide by jet-vapor deposition.
 26. The method of claim 25,wherein the method includes forming the layer of hafnium oxide as aninitial layer of the nanolaminate on the substrate and forming anotherlayer of hafnium oxide as the final layer of the nanolaminate.
 27. Themethod of claim 25, wherein forming a layer of zirconium oxide includesforming a layer of zirconium oxide by jet-vapor deposition at roomtemperature.
 28. The method of claim 25, wherein forming a layer ofhafnium oxide on a substrate by atomic layer deposition using a HfI₄precursor includes pulsing a first oxygen containing precursor into thereaction chamber after pulsing the HfI₄ precursor into the reactionchamber.
 29. The method of claim 28, wherein pulsing a first oxygencontaining precursor includes pulsing a vapor solution of H₂O—H₂O₂. 30.A method of forming a transistor comprising: forming first and secondsource/drain regions in a substrate; forming a body region between thefirst and second source/drain regions; forming a dielectric film abovethe body region between the first and second source/drain regions, thedielectric film having a nanolaminate containing a layer of hafniumoxide and a layer of zirconium oxide; and coupling a gate to thedielectric film, wherein forming the nanolaminate includes: forming thelayer of hafnium oxide by atomic layer deposition using a HfI₄precursor; forming a layer of zirconium oxide on the layer of hafniumoxide, the layer of zirconium oxide formed by a process other thanatomic layer deposition.
 31. The method of claim 30, wherein the methodincludes forming the layer of hafnium oxide as an initial layer of thenanolaminate and forming another layer of hafnium oxide as the finallayer of the nanolaminate.
 32. The method of claim 30, wherein forming alayer of zirconium oxide includes: forming a layer of zirconium on thelayer of hafnium oxide by thermal evaporation; and oxidizing the layerof zirconium using a krypton(Kr)/oxygen(O₂) mixed plasma to form thezirconium oxide layer on the layer of hafnium oxide.
 33. The method ofclaim 30, wherein forming a layer of zirconium oxide includes forming alayer of zirconium oxide by pulsed-laser deposition.
 34. The method ofclaim 30, wherein forming a layer of zirconium oxide includes forming alayer of zirconium oxide by jet-vapor deposition.
 35. The method ofclaim 30, wherein forming a layer of zirconium oxide includes formingthe layer of zirconium oxide by chemical vapor deposition.
 36. Themethod of claim 30, wherein the method includes forming the nanolaminateas a gate dielectric.
 37. The method of claim 30, wherein the methodincludes forming the nanolaminate as a floating gate dielectric.
 38. Amethod of forming a memory comprising: forming a transistor, thetransistor including a dielectric film containing a HfO₂/ZrO₂nanolaminate, the dielectric film formed above a body region between afirst source/drain region and a second source/drain region, theHfO₂/ZrO₂ nanolaminate formed by: forming a layer of hafnium oxide byatomic layer deposition using a HfI₄ precursor; and forming a layer ofzirconium oxide on the layer of hafnium oxide, the layer of zirconiumoxide formed by a process other than atomic layer deposition; forming aword line coupled to a gate of the transistor; forming a source linecoupled to the first source/drain region; and forming a bit line coupledto the second source/drain region.
 39. The method of claim 38, whereinthe method includes forming the layer of hafnium oxide as an initiallayer of the nanolaminate and forming another layer of hafnium oxide asthe final layer of the nanolaminate.
 40. The method of claim 38, whereinforming a layer of zirconium oxide includes: forming a layer ofzirconium on the layer of hafnium oxide by thermal evaporation; andoxidizing the zirconium layer using a krypton(Kr)/oxygen(O₂) mixedplasma to form a zirconium oxide layer on the layer of hafnium oxide.41. The method of claim 38, wherein forming a layer of zirconium oxideincludes forming a layer of zirconium oxide by pulsed-laser deposition.42. The method of claim 38, wherein forming a layer of zirconium oxideincludes forming a layer of zirconium oxide by jet-vapor deposition. 43.The method of claim 38, wherein forming a layer of zirconium oxideincludes forming the layer of zirconium oxide by chemical vapordeposition.
 44. The method of claim 38, wherein the method includesforming a dynamic random access memory.
 45. A method of forming anelectronic system comprising: providing a processor; coupling a memoryto the processor, the memory including a transistor having a dielectricfilm containing a HfO₂/ZrO₂ nanolaminate, the dielectric film formedabove a body region between a first source/drain region and a secondsource/drain region, the HfO₂/ZrO₂ nanolaminate formed by: forming alayer of hafnium oxide by atomic layer deposition using a HfI₄precursor; and forming a layer of zirconium oxide on the layer ofhafnium oxide, the layer of zirconium oxide formed by a process otherthan atomic layer deposition; and providing a bus to couple theprocessor to the memory.
 46. The method of claim 45, wherein the methodincludes forming the layer of hafnium oxide as an initial layer of thenanolaminate and forming another layer of hafnium oxide as the finallayer of the nanolaminate.
 47. The method of claim 45, wherein forming alayer of zirconium oxide includes: forming a layer of zirconium on thelayer of hafnium oxide by thermal evaporation; and oxidizing thezirconium layer using a krypton(Kr)/oxygen(O₂) mixed plasma to form azirconium oxide layer on the layer of hafnium oxide.
 48. The method ofclaim 45, wherein forming a layer of zirconium oxide includes forming alayer of zirconium oxide by pulsed-laser deposition.
 49. The method ofclaim 45, wherein forming a layer of zirconium oxide includes forming alayer of zirconium oxide by jet-vapor deposition.
 50. The method ofclaim 45, wherein forming a layer of zirconium oxide includes formingthe layer of zirconium oxide by chemical vapor deposition.
 51. Themethod of claim 45, wherein the method includes forming an informationhandling system.
 52. The method of claim 51, wherein the method includesforming a wireless system.